1. Field of the Invention
The present invention relates generally to fabrication of ultra-thin bonded semiconductor layers, for electronic applications. In particular, the invention relates to making ultra thin layers for epitaxial growth on a substrate, and for making compliant substrates.
2. Description of the Related Art
Ultra-thin (&lt;10 nm) substrates, including silicon-on-insulator (SOI) substrates, are desirable for many technologies including extreme scaling of MOSFET transistors, dual-gate MOSFETs, quantum wires and dots, and compliant or universal substrates. In the past, ultra-thin semiconductor layers have been produced by successive oxidation and oxide etching of silicon-on-insulator (SOI) wafers. In the oxide thinning technique, an SOI substrate with approximately a 200 nm thick silicon layer is thinned to approximately 50 nm by multiple oxidations and dilute hydrofluoric acid etches. This technique is heavily dependent the thickness uniformity of the SOI silicon layer and the oxidation uniformity. SOI substrates often have a thickness non-uniformity of approximately 10 nm. Thus, the oxidation thinning technique is not suitable for manufacturing ultra-thin (&lt;10 nm) silicon layers.
One method of fabricating silicon-on-insulator (SOI) layer involves bond-and-etch back (BESOI) technique. The BESOI technique involves bonding an etch stop layer to an oxidized silicon handle wafer, thinning the wafer that contains the etch stop layer by grinding, chemically etching to the etch stop layer, and then etching the etch stop layer. A key step in the BESOI process is the method of forming the etch stop layer. A heavily doped (boron concentration &gt;10.sup.20 cm.sup.-3) layer has been used as the etch stop layer. U.S. Pat. No. 5,540,785 to Dennard et al describes a method for making SOI structures using a heavily boron-doped etch stop layer that has a small percentage of germanium added to produce a defect-free epitaxial layer. U.S. Pat. No. 5,013,681 to Godbey et al describes a method to fabricate SOI structures that uses a strained SiGe etch stop. U.S. Pat. No. 5,024,723 to Goesele et al describes a method to fabricate SOI structures by implanting carbon ions into a substrate to form an etch stop layer. The disadvantage of all the BESOI approaches is that the entire host substrate must be removed by a laborious sequence of grinding, polishing, and etching. In addition, overall thickness uniformity during the substrate thinning process must be critically maintained since the etch selectivity of Si over SiGe is limited.
U.S. Pat. No. 5,374,564 to Bruel describes another method of fabricating a silicon-on-insulator (SOI) layer that involves combining wafer bonding with a hydrogen implantation and separation technique. The hydrogen implantation and separation technique utilizes a heavy dose of implanted hydrogen together with subsequent annealing to produce H exfoliation that releases the host substrate to generate the SOI structure. The surface following exfoliation has a microroughness of about 8 nm, and must be given a slight chemomechanical polish to produce a prime surface. This step degrades the Si layer thickness uniformity and makes the process unsuitable for producing very thin Si films.
It has been found experimentally that there are a number of techniques to either reduce the required hydrogen ion implantation dose or to reduce the temperature needed to cause hydrogen ion implantation substrate layer splitting process to work. One technique involves the use of a high pressure nitrogen gas stream directed towards the side of a silicon substrate into which a high dose hydrogen ion implantation has been made. It has been experimentally found that the hydrogen ion implantation substrate layer splitting process can occur at room temperature for the case of a silicon substrate into which a high hydrogen ion implantation dose has been made using the high pressure nitrogen gas stream method. It has also been found experimentally that a helium ion implantation made in combination with a hydrogen ion implantation can be used to achieve a lower total implanted dose for the substrate layer splitting process to occur for a given anneal temperature. It has also been found experimentally that helium ion implantation can be used instead of hydrogen ion implantation for the substrate layer splitting process. It has also been found experimentally that a lower substrate layer splitting temperature is achieved for the case that a hydrogen ion implantation is made into a silicon substrate having a high boron concentration. The high boron concentration can be incorporated into a silicon substrate by ion implantation. The lower temperature for hydrogen ion implantation substrate layer splitting to occur is obtained both for the case that the boron implant is annealed and for the case that the boron implant is unannealed.
Dual-gate MOSFETs have gates located both above and below the conducting channel; a silicon conducting channel with a layer thickness of &lt;10 nm is predicted to be necessary for transistors with conventional lateral dimensions. U.S. Pat. No. 5,273,921 to Neudeck describes a method for fabricating a dual-gate MOSFET that uses the epitaxial lateral overgrowth of mono-crystalline silicon to form the channel. U.S. Pat. No. 5,646,058 to Taur et al describes a method of fabricating a self-aligned double-gate MOSFET by selective lateral epitaxy. U.S. Pat. No. 5,757,038 to Tiwari et al describes a method to fabricate a dual-gate MOSFET that has a vertical conducting channel. The methods for forming a dual-gate transistor involve complicated lateral epitaxial growth.
Ultra-thin semiconductor layers are required for compliant substrates. In structures with a compliant substrate, the ultra-thin semiconductor layer will expand or contract as a heteroepitaxially layer is grown on the surface of the ultra-thin semiconductor layer so that defects, if created, will reside in the ultra-thin semiconductor layer. The principal technique investigated to date for complaint substrate growth is the twist bonding technique and epitaxial growth on SOI substrates with thick (.gtoreq.100 nm) Si films.
An n-channel SiGe Modulation Doped Field Effect Transistors (MODFET) is desirable because of high electron mobility. The n-channel requires a SiGe/Si heterojunction with the offset in the conduction band. To achieve this offset, a structure has been proposed in which a thin silicon layer is strained and the SiGe is relaxed. To fabricate such a structure, a relaxed SiGe buffer layer is required. The approach that has been pursued to date to produce such a relaxed SiGe buffer layer is to grow a stair-cased superlattice of SiGe and Si. The staircase superlattice approach has not been entirely satisfactory because of defects in the superlattice layer.
Thin layers of GaAs have been produced lateral undercutting a AlAs layer and then transferring an epitaxial layer to another substrate, with etch stop techniques. Typically, only small areas (&lt;100 .mu.m square) of thin GaAs can be transferred using the epitaxial lift-off techniques and thus this technique is not suitable for full wafer transfer. In the etch stop technique, the wafer is thinned from the backside to within approximately 50 .mu.m of the etch stop layer and then the GaAs substrate is etched stopping at an AlGaAs etchstop. The AlGaAs etchstop is next etched leaving a thin semiconductor layer. The etch stop technique suffers from non-uniform etching of the etch stop layer.
It is desired to grow arbitrarily thick epitaxial layers on compliant substrates. Lattice mismatch between a compliant substrate and the epitaxial growth layer creates a critical thickness limitation on the growth of the epitaxial layer.